Chiranjeev Singhal Email & Phone Number | With a cumulative experience of 8 years in various capacities I am good in my working domain. I have 4+ years of experience in RTL designing and ASIC verification using System Verilog and SV-UVM. And 1 year of experience in III-V semiconductor fabrication at Wolfson nanotechnology cleanroom as a post graduate researcher. This experience enriched my problem solving capabilities along with my interpersonal skills. Along with considerable 2 years of hands-on work experience in UPF (Low Power) language. Presently, working on various emulation technologies, testing and validation.

Chiranjeev Singhal

With a cumulative experience of 8 years in various capacities I am good in my working domain. I have...
Delhi, Delhi, India

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Chiranjeev Singhal’s Email chiranjeev@dkoplabs.com

Chiranjeev Singhal’s Phone Numbers

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Chiranjeev Singhal’s Location Delhi, Delhi, India

Chiranjeev Singhal’s Current Industry Cadence Design Systems

Chiranjeev Singhal’s Prior Industry Dkop Labs | University Of Leeds

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Principal verification engineer

2024-07-01 00:00:00 - Present

Senior Design Verification Engineer

2019-10-01 00:00:00 - 2020-06-01 00:00:00

Research Assistant

2012-08-01 00:00:00 - 2013-09-01 00:00:00

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Chiranjeev Singhal is a With a cumulative experience of 8 years in various capacities I am good in my working domain. I have 4+ years of experience in RTL designing and ASIC verification using System Verilog and SV-UVM. And 1 year of experience in III-V semiconductor fabrication at Wolfson nanotechnology cleanroom as a post graduate researcher. This experience enriched my problem solving capabilities along with my interpersonal skills. Along with considerable 2 years of hands-on work experience in UPF (Low Power) language. Presently, working on various emulation technologies, testing and validation.