Chintan Patel Email & Phone Number | - 10+ years of experience in ASIC Verification. - Experience on USB 2.0, AMBA AHB, APB, AXI, SMMUv3 protocol. - Practical exposure of working in various phases of Verification IP development. - Experience in RTL Functional Verification and Functional & Code Coverage. - Experience in Constrained Driven Verification (CDV) & regression management. - Hands-on expertise of working on Test Plan & Test bench development in UVM environment - Proficient in writing test cases, simulation and debugging. - Experience in building verification environment from scratch using Verilog, SystemVerilog and methodologies like UVM. - Good Understanding of ASIC Design Flow and Design Verification Techniques.

Chintan Patel

- 10+ years of experience in ASIC Verification. - Experience on USB 2.0, AMBA AHB, APB, AXI, SMMUv3...
Bengaluru, Karnataka, India

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Chintan Patel’s Phone Numbers +91 92422 2****

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Chintan Patel’s Location Bengaluru, Karnataka, India

Chintan Patel’s Current Industry Google

Chintan Patel’s Prior Industry Qualcomm | Intel | Perfectvips | Maven Silicon Softech | Maven Silicon

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Senior Design Verification Engineer

2024-05-01 00:00:00 - Present

Lead Engineer Sr.

2021-06-01 00:00:00 - 2024-05-01 00:00:00

SOC verification engineer

2018-01-01 00:00:00 - 2021-06-01 00:00:00

ASIC verification engineer

2013-11-01 00:00:00 - 2018-01-01 00:00:00

intern

2012-12-01 00:00:00 - 2013-03-01 00:00:00

Asic verification & design trainee

2012-06-01 00:00:00 - 2012-11-01 00:00:00

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Chintan Patel is a - 10+ years of experience in ASIC Verification. - Experience on USB 2.0, AMBA AHB, APB, AXI, SMMUv3 protocol. - Practical exposure of working in various phases of Verification IP development. - Experience in RTL Functional Verification and Functional & Code Coverage. - Experience in Constrained Driven Verification (CDV) & regression management. - Hands-on expertise of working on Test Plan & Test bench development in UVM environment - Proficient in writing test cases, simulation and debugging. - Experience in building verification environment from scratch using Verilog, SystemVerilog and methodologies like UVM. - Good Understanding of ASIC Design Flow and Design Verification Techniques.