Chengjou Liao Email & Phone Number | OBJECTIVE To work in the areas of VLSI, FPGA, or ASIC Design, Verification, and Post-Manufacturing Test. SUMMARY OF QUALIFICATIONS - 5+ years of research and engineering experience in VLSI design, verification, and test, particularly in assertion-based regression and directed testing for hardware functional correctness using Universal/Open Verification Methodology (OVM/UVM). - Extensive programming experience in both hardware description/verification (Verilog, VHDL, SystemVerilog) and software languages (C, C++, Java, Python). - Significant experience with hardware verification (ModelSim, QuestaSim) and test tools (Encounter Test/Diagnosis). - Outstanding communicator and team leader/member who is dedicated to effective progress and completion of team goals.

Chengjou Liao

OBJECTIVE To work in the areas of VLSI, FPGA, or ASIC Design, Verification, and Post-Manufacturing T...
San Jose, California, United States

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Chengjou Liao’s Email chengjou.liao@cavium.com

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Chengjou Liao’s Location San Jose, California, United States

Chengjou Liao’s Current Industry

Chengjou Liao’s Prior Industry Cavium Networks | Lockheed Martin | Advanced Chip Test Laboratory Center For Silicon Systems Implementation Carnegie Mellon University | Ibm | Bechtel Bettis

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Work Experience

Cavium Networks

Senior Engineer

2013-02-01T00:00:00.000Z - 2014-01-01T00:00:00.000Z

Lockheed Martin

ASIC & FPGA Design Engineer

2010-08-01T00:00:00.000Z - 2013-01-01T00:00:00.000Z

Advanced Chip Test Laboratory Center For Silicon Systems Implementation Carnegie Mellon University

Graduate Researcher

2009-05-01T00:00:00.000Z - 2010-08-01T00:00:00.000Z

Ibm

Intern/Co-op

2008-05-01T00:00:00.000Z - 2008-08-01T00:00:00.000Z

Bechtel Bettis

Junior Engineer

2007-08-01T00:00:00.000Z - 2008-01-01T00:00:00.000Z

Skills

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Languages

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FAQ About Chengjou Liao

Chengjou Liao is located at
San Jose, California, United States

Chengjou Liao is a OBJECTIVE To work in the areas of VLSI, FPGA, or ASIC Design, Verification, and Post-Manufacturing Test. SUMMARY OF QUALIFICATIONS - 5+ years of research and engineering experience in VLSI design, verification, and test, particularly in assertion-based regression and directed testing for hardware functional correctness using Universal/Open Verification Methodology (OVM/UVM). - Extensive programming experience in both hardware description/verification (Verilog, VHDL, SystemVerilog) and software languages (C, C++, Java, Python). - Significant experience with hardware verification (ModelSim, QuestaSim) and test tools (Encounter Test/Diagnosis). - Outstanding communicator and team leader/member who is dedicated to effective progress and completion of team goals.

Chengjou Liao currently works in the

No Languages Available

Chengjou Liao has prior
experience in the following industries:
Cavium Networks | Lockheed Martin | Advanced Chip Test Laboratory Center For Silicon Systems Implementation Carnegie Mellon University | Ibm | Bechtel Bettis

Chengjou Liao has the following professional experience:
Cavium Networks | Lockheed Martin | Advanced Chip Test Laboratory Center For Silicon Systems Implementation Carnegie Mellon University | Ibm | Bechtel Bettis