Cesar Mancini Email & Phone Number | Design engineer experienced in high performance microprocessor cores and SOCs, front-end design methodology. Seeking opportunities in logic design, micro-architecture, and design methodology. Interested in work environments that require a broad area of knowledge and problem solving skills. Specialties: Recent experience: VCS, Verilog-XL, Novas Debussy, PowerTheater, Redhawk, Conformal BlackTie, Conformal LEC. Synopsys Design Compiler, Physical Compiler, DFT Compiler. Cadence RTL Compiler, Encounter. Emacs, RCS, DesignSync, LSF. C-shell, Bourne shell, Perl, Make, Tcl, Verilog. PowerPC, M*Core. Unix, Windows. Earlier experience: Cadence: Analog Artist, Spectre, Spectre HDL, Virtuoso, Schematic Composer, DRC, LVS, ERC; Matlab.

Cesar Mancini

Design engineer experienced in high performance microprocessor cores and SOCs, front-end design meth...
4005 Barlow Drive, Round Rock, United States

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Cesar Mancini’s Email cesar.mancini@intel.com

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Cesar Mancini’s Location 4005 Barlow Drive, Round Rock, United States

Cesar Mancini’s Current Industry Intel

Cesar Mancini’s Prior Industry Freescale Semiconductor | Motorola Incfreescale Semiconductor | Motorola | University Of Rochester

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SoC Logic Design Engineer

2007-07-01 00:00:00 - Present

64-bit PowerPC core logic design team

2006-06-01 00:00:00 - 2007-06-01 00:00:00

Dual and single core SoC logic design team

2001-06-01 00:00:00 - 2006-06-01 00:00:00

64-bit PowerPC core logic design team

2000-08-01 00:00:00 - 2001-06-01 00:00:00

Research Associate

1999-06-01 00:00:00 - 2000-03-01 00:00:00

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Cesar Mancini is a Design engineer experienced in high performance microprocessor cores and SOCs, front-end design methodology. Seeking opportunities in logic design, micro-architecture, and design methodology. Interested in work environments that require a broad area of knowledge and problem solving skills. Specialties: Recent experience: VCS, Verilog-XL, Novas Debussy, PowerTheater, Redhawk, Conformal BlackTie, Conformal LEC. Synopsys Design Compiler, Physical Compiler, DFT Compiler. Cadence RTL Compiler, Encounter. Emacs, RCS, DesignSync, LSF. C-shell, Bourne shell, Perl, Make, Tcl, Verilog. PowerPC, M*Core. Unix, Windows. Earlier experience: Cadence: Analog Artist, Spectre, Spectre HDL, Virtuoso, Schematic Composer, DRC, LVS, ERC; Matlab.

Cesar Mancini has prior
experience in the following industries:
Freescale Semiconductor | Motorola Incfreescale Semiconductor | Motorola | University Of Rochester

Cesar Mancini has the following professional experience:
Intel | Freescale Semiconductor | Motorola Incfreescale Semiconductor | Motorola | University Of Rochester