Bhavani Gunda Email & Phone Number | Actively looking for full-time Opportunities in design and verification starting from winter 2024. Being passionate towards design and verification had an hands-on experience in Assertion based verification, Constrained Random ,Stimulus generation, Universal Verification Methodology, reusable test bench architectures, verification plan development and Coverages and implemented simulation of last level cache ,design and implementation of RVfpga SOC based RGB LED -PWM Controller,text editor on target FPGA board, Verification of AMBA AHB 3 LITE protocol-UVM. Simulation of DDR4 Memory controller-system verilog , simulation of MIPS-Lite 5 stage pipeline Architecture(system verilog), Design and verfication of I2C Based memory subsystem in system verilog, and also had an hands-on experience in programming languages-verilog, system verilog , OOPS, Assembly and c and python scripting language and familiar with windows , linux operating system and with formal verification tools like synopsys DC and xilinx vivado, questa sim.

Bhavani Gunda

Actively looking for full-time Opportunities in design and verification starting from winter 2024....
Portland, Oregon, United States

*50 free lookup(s) per month.

Bhavani Gunda’s Email bgunda@pdx.edu

Bhavani Gunda’s Phone Numbers

Get BHAVANI’s Phone Number (For Free)

Social Media

Bhavani Gunda’s Location Portland, Oregon, United States

Bhavani Gunda’s Current Industry Intel Portland State University

Bhavani Gunda’s Prior Industry Society Of Women Engineers | Portland State University Business Accelerator | Samsung | Nsicltd

Find accurate emails & phone numbers for over 700M professionals.

Graduate DFT Engineer Intern

2024-05-01 00:00:00 - Present

Grader for ECE 486/586(COMPUTER ARCHITECTURE)

2024-04-01 00:00:00 - Present

Secretary

2023-09-01 00:00:00 - 2024-04-01 00:00:00

Program Assistant

2022-10-01 00:00:00 - 2024-04-01 00:00:00

Associate Software Engineer

2021-09-01 00:00:00 - 2022-09-01 00:00:00

Intern

2019-05-01 00:00:00 - 2019-07-01 00:00:00

No Skills Available

No Languages Available

Bhavani Gunda is a Actively looking for full-time Opportunities in design and verification starting from winter 2024. Being passionate towards design and verification had an hands-on experience in Assertion based verification, Constrained Random ,Stimulus generation, Universal Verification Methodology, reusable test bench architectures, verification plan development and Coverages and implemented simulation of last level cache ,design and implementation of RVfpga SOC based RGB LED -PWM Controller,text editor on target FPGA board, Verification of AMBA AHB 3 LITE protocol-UVM. Simulation of DDR4 Memory controller-system verilog , simulation of MIPS-Lite 5 stage pipeline Architecture(system verilog), Design and verfication of I2C Based memory subsystem in system verilog, and also had an hands-on experience in programming languages-verilog, system verilog , OOPS, Assembly and c and python scripting language and familiar with windows , linux operating system and with formal verification tools like synopsys DC and xilinx vivado, questa sim.

Bhavani Gunda has prior
experience in the following industries:
Society Of Women Engineers | Portland State University Business Accelerator | Samsung | Nsicltd

Bhavani Gunda has the following professional experience:
Intel | Portland State University | Society Of Women Engineers | Portland State University Business Accelerator | Samsung | Nsicltd