Benoit Specklin Email & Phone Number | 25 years IC development, RQM/CCM and EDA consulting, see specialties. Specialties: RDDF, RQM, CCM, ISO 9001, ISO 26262, FMEA full-custom layout, semi-custom layout (place & route, layout verification, parasitic extraction, timing verification, formal verification), STA, tool migration, library tests, synthesis support, VHDL-design, VHDL Verification, logical synthesis, simulation, interface full-custom / semi-custom, interface synthesis / layout, runsets for layout verification, preparation of IC-block data, design check, software test, physical synthesis, GUI programming, litho-simulation (OPC), Verilog-design, specification-to-VHDL automation

Benoit Specklin

25 years IC development, RQM/CCM and EDA consulting, see specialties. Specialties: RDDF, RQM, CCM,...
Landshut, Landshut, Germany

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Benoit Specklin’s Email benoit@specklin.net

Benoit Specklin’s Phone Numbers +1 408-956-****

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Benoit Specklin’s Location Landshut, Landshut, Germany

Benoit Specklin’s Current Industry Infineon Technologies

Benoit Specklin’s Prior Industry Infineon | Altran | Eurospace | Intel | Siemens

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Senior Manager Operational Excellence RQM / CM

2017-11-01 00:00:00 - Present

digital design, verification, RTL to GDS engineer

2011-06-01 00:00:00 - 2017-10-01 00:00:00

Lead Consultant

2009-01-01 00:00:00 - 2011-06-01 00:00:00

Advanced Consultant

2007-06-01 00:00:00 - 2008-12-01 00:00:00

Silicon DA Manager

2006-06-01 00:00:00 - 2007-01-01 00:00:00

Senior IC Consultant

1999-09-01 00:00:00 - 2005-07-01 00:00:00

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Benoit Specklin is a 25 years IC development, RQM/CCM and EDA consulting, see specialties. Specialties: RDDF, RQM, CCM, ISO 9001, ISO 26262, FMEA full-custom layout, semi-custom layout (place & route, layout verification, parasitic extraction, timing verification, formal verification), STA, tool migration, library tests, synthesis support, VHDL-design, VHDL Verification, logical synthesis, simulation, interface full-custom / semi-custom, interface synthesis / layout, runsets for layout verification, preparation of IC-block data, design check, software test, physical synthesis, GUI programming, litho-simulation (OPC), Verilog-design, specification-to-VHDL automation