Basant Goyal Email & Phone Number | I am working on developing and implementing RTL designs that meet the stringent requirements of Universal Chiplet Interconnect Express (UCIE) protocol. Lead the RTL DESIGN team OF AMS IP (LCPLL, RCOSC, GPIO, etc. ) along with its verification, DFT, UPF Models(multi-voltage design) , integrations with SOC and timing closure. Experienced RTL Lead specializing in IP release process to various customers, LINT, CDC analysis, and VCLP checks. Adept at ensuring design integrity and compliance with industry standards through meticulous verification processes and comprehensive quality assurance practices. Experienced in analog layout design, specializing in creating high-performance, reliable, and manufacturable circuit layouts of Foundational IP's and its automation using SKILL programming language. Experienced in tools and flow methodology/automation using PERL, TCL and UNIX scripting. Deep understanding of system verilog. Tools knowledge: Verdi, Spyglass, virtuoso, git, primetime, vcs etc.

Basant Goyal

I am working on developing and implementing RTL designs that meet the stringent requirements of Univ...
Bengaluru, Bengaluru, India

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Basant Goyal’s Email basant.goyal@intel.com

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Basant Goyal’s Location Bengaluru, Bengaluru, India

Basant Goyal’s Current Industry Intel

Basant Goyal’s Prior Industry Preparing For Ese 2016

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RTL DESIGN ENGINEER

2020-07-01 00:00:00 - Present

Graduate Student

2015-05-01 00:00:00 - 2019-07-01 00:00:00

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Basant Goyal is a I am working on developing and implementing RTL designs that meet the stringent requirements of Universal Chiplet Interconnect Express (UCIE) protocol. Lead the RTL DESIGN team OF AMS IP (LCPLL, RCOSC, GPIO, etc. ) along with its verification, DFT, UPF Models(multi-voltage design) , integrations with SOC and timing closure. Experienced RTL Lead specializing in IP release process to various customers, LINT, CDC analysis, and VCLP checks. Adept at ensuring design integrity and compliance with industry standards through meticulous verification processes and comprehensive quality assurance practices. Experienced in analog layout design, specializing in creating high-performance, reliable, and manufacturable circuit layouts of Foundational IP's and its automation using SKILL programming language. Experienced in tools and flow methodology/automation using PERL, TCL and UNIX scripting. Deep understanding of system verilog. Tools knowledge: Verdi, Spyglass, virtuoso, git, primetime, vcs etc.