Ashish Goel Email & Phone Number | Experience in Semiconductor industry -> Manage SOC RTL and Verification right from Concept to Engineering sample delivery -> Interacting and negotiating with Global teams and ensuring the quality and timely deliverable -> Worked in various domains (laptop, desktop, wireless, networking chips, Graphics, Automotive & Consumer & industrial) -> Lead IP RTL delivery team & Verification and handling multiple IP delivery to multiple SOC -> Well versed with the entire flow from concept to qualification -> Experience in various flavors of verification like ABV, Formal Verification and Coverage driven random verification, Low Power Verification, GLS -> Worked on Macro, Micro architecture, RTL design & Support Validation (pre & post silicon) -> Provide solution to organization verification challenges -> Identifying/Implementing the methodology changes to increase productivity Specialties: Languages: C, C++, VHDL, Verilog, System Verilog, Vera,Perl,TCL, Shell, Makefiles Other Tools: Perforce, Clearcase, Design Sync, Certitude, HAL, CDC Methodologies: Formal, Functional, Low power, Assertion Based verification, UVM, GLS Knowledge in standard like DDR , 802.11a, JTAG, DIGRF, PCI, AHB, AXI Flash & various other peripherals IPs

Ashish Goel

Experience in Semiconductor industry -> Manage SOC RTL and Verification right from Concept to Engin...
Noida, Noida, India

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Ashish Goel’s Email ashish.goel@nxp.com

Ashish Goel’s Phone Numbers +1 408-434-****

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Ashish Goel’s Location Noida, Noida, India

Ashish Goel’s Current Industry Nxp Semiconductors

Ashish Goel’s Prior Industry Amd | Freescale Semiconductors | Transwitch | Dcm Technologies

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Senior Principal Engineer

2017-06-01 00:00:00 - Present

Manager

2012-05-01 00:00:00 - 2017-06-01 00:00:00

Verification Lead Engineer

2005-11-01 00:00:00 - 2012-05-01 00:00:00

Mts

2003-12-01 00:00:00 - 2005-11-01 00:00:00

Design Engineer

2000-07-01 00:00:00 - 2003-12-01 00:00:00

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Ashish Goel is a Experience in Semiconductor industry -> Manage SOC RTL and Verification right from Concept to Engineering sample delivery -> Interacting and negotiating with Global teams and ensuring the quality and timely deliverable -> Worked in various domains (laptop, desktop, wireless, networking chips, Graphics, Automotive & Consumer & industrial) -> Lead IP RTL delivery team & Verification and handling multiple IP delivery to multiple SOC -> Well versed with the entire flow from concept to qualification -> Experience in various flavors of verification like ABV, Formal Verification and Coverage driven random verification, Low Power Verification, GLS -> Worked on Macro, Micro architecture, RTL design & Support Validation (pre & post silicon) -> Provide solution to organization verification challenges -> Identifying/Implementing the methodology changes to increase productivity Specialties: Languages: C, C++, VHDL, Verilog, System Verilog, Vera,Perl,TCL, Shell, Makefiles Other Tools: Perforce, Clearcase, Design Sync, Certitude, HAL, CDC Methodologies: Formal, Functional, Low power, Assertion Based verification, UVM, GLS Knowledge in standard like DDR , 802.11a, JTAG, DIGRF, PCI, AHB, AXI Flash & various other peripherals IPs