Anurag Verma Email & Phone Number | As a Physical Design Engineer my work involves- 1. Converging complex partitions of latest gen-graphics core with multi-million gate count for timing and shorts as Partition Execution Owner (PEO) of 14nm Technology node. 2. Converging partitions includes the synthesized Netlist to GDS-II file through the Placement, CTS, Routing and Post Route Flow. 3. PnR flow execution using Synopsys Design Compiler and IC compiler. 4. Implementing functional ECO including swap, buffer insertion and rerouting nets. 5. Layout Verification (DRC, LVS, Antenna Violation, Density Issues) on Synopsys icv tool. 6. Tape-in 3 partition for 14nm technology node.

Anurag Verma

As a Physical Design Engineer my work involves- 1. Converging complex partitions of latest gen-graph...
India

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Anurag Verma’s Email anurag.verma@intel.com

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Anurag Verma’s Location India

Anurag Verma’s Current Industry Intel

Anurag Verma’s Prior Industry All India Radio | Cetpa Infotech

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Graphic Hardware Engineer

2015-09-01 00:00:00 - Present

Trainee

2011-06-01 00:00:00 - 2011-07-01 00:00:00

Trainee

2010-06-01 00:00:00 - 2010-07-01 00:00:00

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Anurag Verma is a As a Physical Design Engineer my work involves- 1. Converging complex partitions of latest gen-graphics core with multi-million gate count for timing and shorts as Partition Execution Owner (PEO) of 14nm Technology node. 2. Converging partitions includes the synthesized Netlist to GDS-II file through the Placement, CTS, Routing and Post Route Flow. 3. PnR flow execution using Synopsys Design Compiler and IC compiler. 4. Implementing functional ECO including swap, buffer insertion and rerouting nets. 5. Layout Verification (DRC, LVS, Antenna Violation, Density Issues) on Synopsys icv tool. 6. Tape-in 3 partition for 14nm technology node.