Ankit Dwivedi Email & Phone Number | Graduate Student at University Of Sothern California, Los Angeles. Seeking Full-Time(starting June 2015) in the areas of Computer Architecture/RTL design/ ASIC design/Digital VLSI design/Physical Design, verification and testing. I am well versed with Python and Verilog coding along with the essential concepts related to digital systems design (CMOS design). I have also hands-on experience with EDA tools like Synopsys DC compiler, PrimeTime, Cadence Encounter (for PAR). I would like to use the knowledge gained in my course work at USC for this position and also in the process would learn some thing new every day. Skills: CACTI6.5 to find the RAM/CACHE design with optimum power, delay and area for YIELD improvement, Logic Synthesis with Xilinx ISE/Synopsis Design Compiler, Schematic/Layout design in Cadence Virtuoso, Verilog/VHDL coding in ModelSim/NC-Verilog, C/C++/C# Programming, PERL and Python Scripting, APR using Cadence Encounter and STA using PrimeTime HDL and Programming Languages : Verilog, System C, C, C++, VHDL Tools and Packages : ModelSim, Cadence Virtuoso, Xilinx 14.7, NCsim, dccompiler, PrimeTime, Cadence Encounter, Microsoft Visual Studio, Eclipse. Scripting : Perl, Python Web Page : www.googledrive.com/host/0B47ai8H-zYjWVGhlR09tVFFKZmM

Ankit Dwivedi

Graduate Student at University Of Sothern California, Los Angeles. Seeking Full-Time(starting June 2...
San Diego, California, United States

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Ankit Dwivedi’s Email adwivedi@qualcomm.com

Ankit Dwivedi’s Phone Numbers +1 858-651-****

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Ankit Dwivedi’s Location San Diego, California, United States

Ankit Dwivedi’s Current Industry Qualcomm

Ankit Dwivedi’s Prior Industry University Of Southern California | Usc Dana And David Dornsife College Of Arts Letters And Sciences | Infosys

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Senior Product Test Engineer

2019-11-01 00:00:00 - Present

Admission Processing

2014-06-01 00:00:00 - 2014-12-01 00:00:00

Web Developer

2014-05-01 00:00:00 - 2014-06-01 00:00:00

Systems Engineer

2012-02-01 00:00:00 - 2013-07-01 00:00:00

No Skills Available

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Ankit Dwivedi is a Graduate Student at University Of Sothern California, Los Angeles. Seeking Full-Time(starting June 2015) in the areas of Computer Architecture/RTL design/ ASIC design/Digital VLSI design/Physical Design, verification and testing. I am well versed with Python and Verilog coding along with the essential concepts related to digital systems design (CMOS design). I have also hands-on experience with EDA tools like Synopsys DC compiler, PrimeTime, Cadence Encounter (for PAR). I would like to use the knowledge gained in my course work at USC for this position and also in the process would learn some thing new every day. Skills: CACTI6.5 to find the RAM/CACHE design with optimum power, delay and area for YIELD improvement, Logic Synthesis with Xilinx ISE/Synopsis Design Compiler, Schematic/Layout design in Cadence Virtuoso, Verilog/VHDL coding in ModelSim/NC-Verilog, C/C++/C# Programming, PERL and Python Scripting, APR using Cadence Encounter and STA using PrimeTime HDL and Programming Languages : Verilog, System C, C, C++, VHDL Tools and Packages : ModelSim, Cadence Virtuoso, Xilinx 14.7, NCsim, dccompiler, PrimeTime, Cadence Encounter, Microsoft Visual Studio, Eclipse. Scripting : Perl, Python Web Page : www.googledrive.com/host/0B47ai8H-zYjWVGhlR09tVFFKZmM

Ankit Dwivedi has prior
experience in the following industries:
University Of Southern California | Usc Dana And David Dornsife College Of Arts Letters And Sciences | Infosys

Ankit Dwivedi has the following professional experience:
Qualcomm | University Of Southern California | Usc Dana And David Dornsife College Of Arts Letters And Sciences | Infosys