Anand Kumar Email & Phone Number | Master’s Degree and 11+ years of experience with ASIC/SOC front end Design ,verification and EDA Methodology development along with FPGA/Board Design and validation. -Significant experience with all stages of Front-end IC Design including RTL Compile, RTL Rule check, Synthesis , Netlist generation, Equivalence check and coverage. -ASIC Design & Verification EDA flow & methodology development, setup, customization and management. - Experience in HW, Board bring-up , Pre-post SI analysis and Compliance testing Activities. -Good understanding of System architecture/design concepts, Memory interfaces , -Proficient in Hardware and HW-SW interfacing concepts and for the board bring-up activities and resolution of critical system level issues consistently in projects which required both HW and SW understanding. Specialties: EDA tools: Modelsim, VCS, NCSim, DVE, SimVision, Specman, SpyGlass, Synopsys Design Compiler, Cadence LEC, Xilinx ISE 10.1,Quartus II , SCHEMATIC TOOL ,SI (ICX) HDLs / HVLs /Protocols: VHDL, Verilog, , Specman E, PCIE 3.0, AMBA ,AXI Programming Languages: “C”, Perl, TCL, , Makefile Platforms / CM Tools: Windows, SOLARIS, Linux, UNIX, MS Office, ClearCase Digital FPGA /System Design Signal Integrity Analysis. Hardware Testing and integration. Positive Attitude & self confidence

Anand Kumar

Master’s Degree and 11+ years of experience with ASIC/SOC front end Design ,verification and EDA M...
Bengaluru, Karnataka, India

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Anand Kumar’s Email anand.kumar@intc.com

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Anand Kumar’s Location Bengaluru, Karnataka, India

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Anand Kumar’s Prior Industry Qualcomm | Tata Elxsi | Wipro Technologies | Drdo

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Soc Design Eng Manager

2019-10-01 00:00:00 - Present

Staff Engineer

2014-11-01 00:00:00 - 2019-10-01 00:00:00

Specialist

2011-08-01 00:00:00 - 2012-08-01 00:00:00

Vlsi Design And Eda Front End Verification Methodology Engineer

2010-10-01 00:00:00 - 2011-07-01 00:00:00

Project Trainee

2002-01-01 00:00:00 - 2003-01-01 00:00:00

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Anand Kumar is a Master’s Degree and 11+ years of experience with ASIC/SOC front end Design ,verification and EDA Methodology development along with FPGA/Board Design and validation. -Significant experience with all stages of Front-end IC Design including RTL Compile, RTL Rule check, Synthesis , Netlist generation, Equivalence check and coverage. -ASIC Design & Verification EDA flow & methodology development, setup, customization and management. - Experience in HW, Board bring-up , Pre-post SI analysis and Compliance testing Activities. -Good understanding of System architecture/design concepts, Memory interfaces , -Proficient in Hardware and HW-SW interfacing concepts and for the board bring-up activities and resolution of critical system level issues consistently in projects which required both HW and SW understanding. Specialties: EDA tools: Modelsim, VCS, NCSim, DVE, SimVision, Specman, SpyGlass, Synopsys Design Compiler, Cadence LEC, Xilinx ISE 10.1,Quartus II , SCHEMATIC TOOL ,SI (ICX) HDLs / HVLs /Protocols: VHDL, Verilog, , Specman E, PCIE 3.0, AMBA ,AXI Programming Languages: “C”, Perl, TCL, , Makefile Platforms / CM Tools: Windows, SOLARIS, Linux, UNIX, MS Office, ClearCase Digital FPGA /System Design Signal Integrity Analysis. Hardware Testing and integration. Positive Attitude & self confidence