Aloysius Abreo Email & Phone Number | Current working at Nvidia as a Senior Physical Design Engineer. I am a graduate from Georgia Institute of Technology, Atlanta, USA with a Masters degree in Electronics and Computer Engineering. My focused specialization is VLSI systems and Computer Architecture Design. As a physical design engineer, I have worked on various aspects of the ASIC design flow ranging from design synthesis to place and route, timing convergence, power optimization and full-chip STA analysis/closure of advanced node designs. My prior industry experience also includes the design of reference platform designs for client SoC validation.

Aloysius Abreo

Current working at Nvidia as a Senior Physical Design Engineer. I am a graduate from Georgia Institu...
United States

*50 free lookup(s) per month.

Aloysius Abreo’s Email aloysiusabreo@gatech.edu

Aloysius Abreo’s Phone Numbers

Get ALOYSIUS’s Phone Number (For Free)

Social Media

Aloysius Abreo’s Location United States

Aloysius Abreo’s Current Industry Nvidia

Aloysius Abreo’s Prior Industry Georgia Institute Of Technology | Apple | Intel | Bhabha Atomic Research Centre | Reliance Communications

Find accurate emails & phone numbers for over 700M professionals.

Senior Physical Design and Timing Engineer

2023-06-01 00:00:00 - Present

Graduate Student

2021-08-01 00:00:00 - 2023-05-01 00:00:00

CPU Design Intern

2022-08-01 00:00:00 - 2022-12-01 00:00:00

ASIC Physical Design Engineer

2017-12-01 00:00:00 - 2021-07-01 00:00:00

Summer Intern

2015-05-01 00:00:00 - 2015-07-01 00:00:00

Summer Intern

2014-05-01 00:00:00 - 2014-07-01 00:00:00

No Skills Available

No Languages Available

Aloysius Abreo is a Current working at Nvidia as a Senior Physical Design Engineer. I am a graduate from Georgia Institute of Technology, Atlanta, USA with a Masters degree in Electronics and Computer Engineering. My focused specialization is VLSI systems and Computer Architecture Design. As a physical design engineer, I have worked on various aspects of the ASIC design flow ranging from design synthesis to place and route, timing convergence, power optimization and full-chip STA analysis/closure of advanced node designs. My prior industry experience also includes the design of reference platform designs for client SoC validation.

Aloysius Abreo has prior
experience in the following industries:
Georgia Institute Of Technology | Apple | Intel | Bhabha Atomic Research Centre | Reliance Communications

Aloysius Abreo has the following professional experience:
Nvidia | Georgia Institute Of Technology | Apple | Intel | Bhabha Atomic Research Centre | Reliance Communications