Akash Jain Email & Phone Number | ASIC/ FPGA Engineer specializing in HSIO validation (USB3.x, PCIe, Thunderbolt and USB4) including Type-C Subsystem. Incharge of integrating complex RTL design, timing convergence and complete validation on the FPGA and Emulators. Responsible for designing special RTL blocks to provide specific feature validation. Managing Cross-Functional teams across sites (USA, India, Malaysia, China and Israel) Specialties: Logic / RTL Design, FPGA Early Prototyping, Simics Emulation, System Verilog, Debugging & Digital Logic Designer, Testchip Methodology and Validation, System Validation Xilinx, Vivado, Protocompiler, Synopsys HAPS, Various Scripting languages & RTL USBx and PCIe High Speed IO IP Owner

Akash Jain

ASIC/ FPGA Engineer specializing in HSIO validation (USB3.x, PCIe, Thunderbolt and USB4) including...
900 Bullion Lane, Folsom, United States

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Akash Jain’s Email akash.jain@intel.com

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Akash Jain’s Location 900 Bullion Lane, Folsom, United States

Akash Jain’s Current Industry Intel

Akash Jain’s Prior Industry University Of Southern California | Siemens Enterprise Communications | Ashida Electronics | Tei Technologies

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USB-C Early Prototyping Engineering Tech Lead

2023-01-01 00:00:00 - Present

Research Student Assistant

2012-08-01 00:00:00 - 2013-01-01 00:00:00

Technical Trainee

2010-08-01 00:00:00 - 2011-05-01 00:00:00

Internsihp

2010-06-01 00:00:00 - 2010-08-01 00:00:00

Internsihp

2009-06-01 00:00:00 - 2009-08-01 00:00:00

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Akash Jain is a ASIC/ FPGA Engineer specializing in HSIO validation (USB3.x, PCIe, Thunderbolt and USB4) including Type-C Subsystem. Incharge of integrating complex RTL design, timing convergence and complete validation on the FPGA and Emulators. Responsible for designing special RTL blocks to provide specific feature validation. Managing Cross-Functional teams across sites (USA, India, Malaysia, China and Israel) Specialties: Logic / RTL Design, FPGA Early Prototyping, Simics Emulation, System Verilog, Debugging & Digital Logic Designer, Testchip Methodology and Validation, System Validation Xilinx, Vivado, Protocompiler, Synopsys HAPS, Various Scripting languages & RTL USBx and PCIe High Speed IO IP Owner

Akash Jain has prior
experience in the following industries:
University Of Southern California | Siemens Enterprise Communications | Ashida Electronics | Tei Technologies

Akash Jain has the following professional experience:
Intel | University Of Southern California | Siemens Enterprise Communications | Ashida Electronics | Tei Technologies