Aditya Gulkotwar Email & Phone Number | 7.5+ yrs of experience as Verification Engineer. MS in Electrical Engineering from San Jose State Engineering. TECHNICAL SKILLS: Computer Languages: C, C++ Hardware Description Language: SystemVerilog, Verilog, VHDL Tools: Cadence - Xcelium, Simvision, IMC, Profiler, JasperGold (FPV, Connectivity) Synopsys - Verdi, Verdi HW/SW debugger, VCS, URG, VC Formal (VC_SEQ) Simulation Verification: UVM, Assertion based Verification, Constrained Random Stimulus Generation, Functional Coverage Driven Verification, UVM RAL Formal Verification: Formal Property verification, Connectivity checking, Sequential Clock-gate verification Bus Protocols: AXI, APB, AHB, I2C Scripting Language: Shell, Python, TCL ASIC/SOC Design: Static Timing Analysis, RTL Design, Pipelining, Logic Synthesis, Scan Chain, D-Algorithm, Design-for-Test(DFT) Embedded Systems: 8051, ATMEGA AVR, Arduino Duemilanove, ARM 7 (LPC2148) Assembly Language: INTEL-8085, 8086, 8051

Aditya Gulkotwar

7.5+ yrs of experience as Verification Engineer. MS in Electrical Engineering from San Jose State En...
Austin, Texas, United States

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Aditya Gulkotwar’s Email gulkotwara@amazon.com

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Aditya Gulkotwar’s Location Austin, Texas, United States

Aditya Gulkotwar’s Current Industry Nvidia

Aditya Gulkotwar’s Prior Industry Amazon Web Services | Cirrus Logic | San Jose State University | Granite River Labs

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Senior Design Verification Engineer

2024-06-01 00:00:00 - Present

Design Verification Engineer

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Design Verification Engineer

2017-02-01 00:00:00 - 2020-02-01 00:00:00

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2014-08-01 00:00:00 - 2016-12-01 00:00:00

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2016-03-01 00:00:00 - 2016-05-01 00:00:00

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Aditya Gulkotwar is a 7.5+ yrs of experience as Verification Engineer. MS in Electrical Engineering from San Jose State Engineering. TECHNICAL SKILLS: Computer Languages: C, C++ Hardware Description Language: SystemVerilog, Verilog, VHDL Tools: Cadence - Xcelium, Simvision, IMC, Profiler, JasperGold (FPV, Connectivity) Synopsys - Verdi, Verdi HW/SW debugger, VCS, URG, VC Formal (VC_SEQ) Simulation Verification: UVM, Assertion based Verification, Constrained Random Stimulus Generation, Functional Coverage Driven Verification, UVM RAL Formal Verification: Formal Property verification, Connectivity checking, Sequential Clock-gate verification Bus Protocols: AXI, APB, AHB, I2C Scripting Language: Shell, Python, TCL ASIC/SOC Design: Static Timing Analysis, RTL Design, Pipelining, Logic Synthesis, Scan Chain, D-Algorithm, Design-for-Test(DFT) Embedded Systems: 8051, ATMEGA AVR, Arduino Duemilanove, ARM 7 (LPC2148) Assembly Language: INTEL-8085, 8086, 8051

Aditya Gulkotwar has prior
experience in the following industries:
Amazon Web Services | Cirrus Logic | San Jose State University | Granite River Labs

Aditya Gulkotwar has the following professional experience:
Nvidia | Amazon Web Services | Cirrus Logic | San Jose State University | Granite River Labs