Aarti Ramesh Email & Phone Number | Physical Design Engineer with 10 years of professional experience involving multiple tapeouts in advanced FinFET technology nodes such as 14nm, 10nm and 7nm. Strong background in all stages of ASIC physical design flow - Floorplanning, power planning, place and route, clock tree synthesis, static timing analysis, EM/IR analysis and physical verification.

Aarti Ramesh

Physical Design Engineer with 10 years of professional experience involving multiple tapeouts in adv...
Menlo Park, California, United States

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Aarti Ramesh’s Email aarti@meta.com

Aarti Ramesh’s Phone Numbers +1 859-223-****

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Aarti Ramesh’s Location Menlo Park, California, United States

Aarti Ramesh’s Current Industry Meta

Aarti Ramesh’s Prior Industry Innovium | Qualcomm | Intel | Beroe

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Technical Lead - Physical Design

2018-07-01 00:00:00 - 2019-01-01 00:00:00

Senior Engineer

2015-11-01 00:00:00 - 2018-07-01 00:00:00

Design Engineering Intern

2012-01-01 00:00:00 - 2012-12-01 00:00:00

Research Analyst

2009-12-01 00:00:00 - 2010-05-01 00:00:00

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Aarti Ramesh is a Physical Design Engineer with 10 years of professional experience involving multiple tapeouts in advanced FinFET technology nodes such as 14nm, 10nm and 7nm. Strong background in all stages of ASIC physical design flow - Floorplanning, power planning, place and route, clock tree synthesis, static timing analysis, EM/IR analysis and physical verification.